Ŀ ְ ϶ϰ ־ . 10 1 26 Ŀ 0.8%(25) 3070 ̴. ְ ǥ(5 14) 3660 3 16% ϶ߴ.
14 ǥ Ŀ 1б 232 67.3%(94) þ. 26 72.3%, 21 88.9% ߴ.
PLD ݵü ݵü ǰ ̲ Ǯ̵ȴ. ݵü ǰ 225 (130) 95(73.1%) ߴ. Ŀ ݵü ݵü ǰ 97% Ѵ.
262000 (152000) 72.9% þ ȸߴ. ߴ 12000 ش ϵ ʴ 1б ǰ 12.5% þ ǰ (67.3%) ũ ƴ. ǰ 8.6% 4.2%P þ.
205000 88.9% þ. ȭ ø鼭 Ÿ -3000 (-3) 27000 ƴ. 300 13000 ߴ.
Ŀ ݵü PLD(Programmable Logic Device) ݵü Ƴα ݵü Ѵ. ؿ ݵü ü ϸ(Xilinx), ͽ(Intersil) Ʈʷ ϰ 500 ITü ǰ ǰϰ ִ.
Ŀ 50~55% ϴ PLDݵü ü ϸ(Xilinx) ް üϰ ִ. ַ ǰ Xilinx PLD α ֹ ݵü ڰ Ӱ ݵü Ĩ ϴ ϰ ־ ǰ ߿ ҿǴ ð ִ.
1б ݿ Ŀ ְ(PER) 8.23. ְڻ(PBR) 1.25, ڱںͷ(ROE) 15.1%.
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